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fix: x86 JIT remw returns stale RDX for i32::MIN % -1 - #3010

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rkm0959 merged 1 commit into
succinctlabs:mainfrom
MatusKysel:fix/jit-remw-overflow
Oct 19, 2026
Merged

rkm0959 merged 1 commit into
succinctlabs:mainfrom
MatusKysel:fix/jit-remw-overflow

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Motivation

The x86-64 JIT backend special-cases i32::MIN % -1 in remw because idiv would raise #DE for that operand pair. The special-case branch was copied from divw: it writes i32::MIN to RAX, but remw stores its result from RDX, so rd receives whatever RDX happened to hold. The overflow: block that zeroes RDX sits after an unconditional jmp and is unreachable.

RISC-V defines remw of -2^31 by -1 as 0, and that is what the portable executor, the tracing VM and the AIR compute. On x86-64 Linux hosts (sp1_use_native_executor) the native executor therefore returns a wrong register value for this one operand pair: execute() reports wrong public values, and when the wrong value reaches memory the trace no longer matches the executor's memory oracle and proving fails. Safe Rust cannot reach it (% on this pair panics even with overflow checks off, and the wrapping/checked variants guard it before the instruction), but C or inline assembly can, and the 64-bit rem as well as div/divw already handle the same pair correctly.

Found by differential fuzzing of the native executor against the portable executor, the tracing-VM replay and an independent RV64IM model; this was the only divergence across the RV64IM instruction set.

Solution

Write the zero remainder to RDX on the overflow path and drop the unreachable block. No other code path changes.

Tests added in the x86 backend test suite for the i32::MIN / -1 pair on remw (immediate and register forms) and divw. The remw test first leaves a non-zero remainder in RDX so a stale-register result fails deterministically rather than by chance. On x86-64 Linux the new remw test fails on main and passes with the fix; the rest of the sp1-jit suite is unaffected.

PR Checklist

  • Added Tests
  • Added Documentation
  • Breaking changes

The overflow special case in the x86 backend's `remw` was copied from
`divw` and leaves its result in RAX, while `remw` stores `rd` from RDX.
The `overflow:` block that zeroes RDX sits behind an unconditional jump
and is unreachable, so `rd` received whatever RDX held. RISC-V defines
`remw(-2^31, -1)` as 0, which the portable executor, the tracing VM and
the AIR already compute, so the native executor diverged from them on
this operand pair.

Write the zero remainder to RDX directly, drop the dead block, and add
regression tests for the `remw` and `divw` overflow pair in both
immediate and register forms.

@rkm0959 rkm0959 left a comment

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Thanks for the PR! LGTM.

@rkm0959
rkm0959 merged commit 40deb33 into succinctlabs:main Oct 19, 2026
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2 participants